The present application relates to semiconductor technology, and more particularly, to a semiconductor structure containing a reliable interconnect structure in which the via profile/geometry is well controlled. The present application also provides a method of making such a semiconductor structure.
Generally, semiconductor devices include a plurality of circuits that form an integrated circuit (IC) fabricated on a semiconductor substrate. A complex network of signal paths will normally be routed to connect the circuit elements distributed on the surface of the substrate. Efficient routing of these signals across the device requires formation of multilevel or multilayered schemes, such as, for example, single or dual damascene wiring structures. The wiring structure, which may also be referred to as an interconnect structure, typically includes copper, Cu, since Cu based interconnects provide higher speed signal transmission between large numbers of transistors on a complex semiconductor chip as compared with aluminum, Al, based interconnects.
Within a typical interconnect structure, metal vias run perpendicular to the semiconductor substrate and metal lines run parallel to the semiconductor substrate. Further enhancement of the signal speed and reduction of signals in adjacent metal lines (known as “crosstalk”) are achieved in today's IC product chips by embedding the metal lines and metal vias (e.g., conductive features) in a dielectric material having a dielectric constant of less than 4.0 (i.e., a low k dielectric material).
One challenge facing current interconnect structures is that a large tapered via profile can lead to unwanted shorts to underlying and/or overlying metal lines. These shorts, in turn, can degrade the performance and reliability of the interconnect structure. As such, there is a need for providing an interconnect structure in which the via profile/geometry is sufficiently controlled so as to avoid the formation of a large tapered via profile.